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FUJITSU SEMICONDUCTOR DATA SHEET
DS04-22415-1E
ASSP
CMOS
Communication Control
SCSI-II Protocol Controller
(with single-ended driver/receiver)
MB86604L
s DESCRIPTION
The Fujitsu MB86604L is a single-ended transmission type SCSI-II Protocol Controller (SPC) with a single-ended driver/receiver. The MB86604L facilitates interface control between small/medium host computer and peripheral devices (such as a hard disk and printer). The specifications conform to the SCSI-II Standard. The MB86604L supports high-speed synchronous transfer, the MPU/DMA independent system data bus, and user programmable command set to enable configuration of high-performance systems. It can also have the phase-to-phase sequence control function to reduce the program overhead of the host MPU. The MB86604L incorporate with a single-ended type SCSI driver/receiver which can drive 48 mA of large-current, and so, the device can be directly connected with the SCSI bus. The device can operate with +5 V single-power supply and in up to 40 MHz clock frequency. As for package, a 100-pin plastic small quad flat package is available.
s FEATURES
SCSI Bus Interface: * Conforming to the SCSI-II standard * Operatable as Initiator and target
(Continued)
s PACKAGE
100 pin, Plastic LQFP
(FPT-100P-M05)
MB86604L
(Continued)
* Two types of high-speed data transfer: - Synchronous data transfer (Max. 10 Mbytes/s, max. 32 offsets, 32-step transfer rate) - Asynchronous data transfer (Max. 5 Mbyte/s) * Transfer parameters (transfer mode, transfer rate, transfer offset) can be set for up to 7 connected devices. * Single-ended transmission type (Maximum cable length: 6 m): - On-chip single-ended driver/receiver which can drive 48 mA of "L" level output current - Directly connectable with the SCSI bus * On-chip three-state bidirectional I/O buffers for SCSI REQ and ACK pins (DB7-DB0, DBP ATN, MSG, C/D, I/ , O pins can be selected from either three-state or open-drain buffer by controlling the TEST pins input.) Transfer Operation: * Automatic response to selection/reselection (Preset receiving operation can perform at the selection/ reselection.): - Initiator: Automatically operates until message received without command issue. - Target: Automatically operates until command received without command issue. * Automatic receiving: - Initiator: Automatically receives information for new phase to which target transited without command issue. - Target: Automatically receives message from initiator when initiator generates attention condition. * On-chip 32-byte data register (FIFO) for data phase * On-chip two (send-only and receive-only) 32-byte data buffers for message, command, and status phases * On-chip 16-bit transfer block register and 24-bit transfer byte register enabling 1 Tbytes transfer (1 Tbytes: 16 Mbytes x 64 k blocks) * On-chip independent data transfer bus enabling the MPU operation during the data transfer * Parity through/generate can be specified. System Bus Interface: * 8-bit or 16-bit separate MPU and DMA buses * Directly connectable with a 80 series or 68 series MPU * Two types of transfer operation: - Program transfer - DMA transfer (Burst/Handshake) Command Set: * Supports sequential commands and programmable commands in addition to ordinary commands * Command queuing (Command can be continuously issued by putting tags to commands in command phase.) * On-chip 256-byte memory for command programming memory and command queuing buffer Others * Process: CMOS process * Supply Voltage: Single +5 V * Input System Clock: 20 MHz/30 MHz/40 MHz * Package: 100-pin plastic LQFP
2
MB86604L
s PIN ASSIGNMENT
(TOP VIEW) WR RD V DD V SS CLK RESET INT MODE DBP V SS DB 7 DB 6 DB 5 V DD V SS V SS DB 4 DB 3 DB 2 DB 1 V SS DB 0 TEST 1 TMOUT (OPEN) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 BHE UDP D 15 D 14 D 13 D 12 D 11 D 10 D9 D8 V SS D7 D6 D5 D4 D3 D2 D1 D0 LDP CS 1 V SS V DD CS 0 A4
I OWR I ORD V DD V SS DMA 0 LDMDP DMD 0 DMD 1 DMD 2 DMD 3 DMD 4 DMD 5 DMD 6 DMD 7 V SS DMD 8 DMD 9 DMD 10 DMD 11 DMD 12 DMD 13 DMD 14 DMD 15 UDMDP DMBHE
INDEX 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A3 A2 A1 A0 ATN V SS BSY ACK RST V SS V SS V DD MSG SEL C/D REQ V SS I/O TEST2 (OPEN) TP V SS V DD DREQ DACK (FPT-100P-M05)
3
MB86604L
s PIN DESCRIPTION
1. SCSI Interface
Pin number 60 Symbol REQ Pin name Request I/O I/O Function Transfer request signal in the information transfer phases from target to initiator. The input signal to this pin is used for the timing control of data transfer sequence. This is a three-state I/O pin and an active low pin. This pin is for the acknowledge signal from initiator to target for the REQ signal in the information transfer phases. The input signal to this pin is used for the timing control of data transfer sequence. This is a three-state I/O pin and an active low pin. This pin is for the attention signal that initiator requests target for the message transfer phase. This is an active-low pin. This pin is for the message signal that specifies type of information transferred on the data bus. This is an active-low pin and becomes "L" when message phase is specified. This pin is for the control/data signal that specifies type of information transferred on the data bus. This an active-low pin and becomes "L" level when command, status, or message phase is specified. This pin is for the input/output signal that specifies direction of information transferred on the data bus. This is an active-low pin. When this pin is "L" level, the information is transferred from target to initiator. When this pin is "H" level, the information is transferred from initiator to target. This pin is for the SCSI bus busy signal. In the arbitration phase, this is for the request signal for the use of bus acquisition. This is an active-low pin. This pin is for the select signal used by initiator to select target during the selection phase and by target to reselect initiator during the reselection phase. This is an active-low pin. This pin is for the reset signal used by any device on the bus. When the device is an input operation, the reset signal is input to this pin. When output operation, the reset signal is output from this pin. This is an active-low pin. These pins are for the bidirectional 8-bit SCSI data bus and 1-bit odd parity line.
68
ACK
Acknowledge
I/O
71 63
ATN MSG*
Attention Message
I/O I/O
61
C/D*
Control/data
I/O
58
I/O*
Input/output
I/O
69
BSY
Busy
I/O
62
SEL
Select
I/O
67
RST
Reset
I/O
11, 12, 13, DB7 17, 18, 19, to DB0 20, 22 9 DBP
Data bus 7 to data bus 0 Data bus parity
I/O
* : Regarding the status of information transfer which is indicated by MSG, C/D, and I/O pins, See Table Phase Status.
4
MB86604L
Phase name Data-out phase Data-in phase Command phase Status phase Message-out phase Message-in phase
MSG H H H H L L
C/D H H L L L L
I/O H L H L H L
Transfer direction Initiator Target
Note: The SCSI interface input/output pins can be connected to a single-end type SCSI bus.
2. MPU Interface
Pin number 77 80 Symbol* CS0 CS1 Pin name Chip select 0 Chip select 1 Data 15 to data 8 Upper data parity Data 7 to data 0 Lower data parity Address 4 to address 0 Read (read/write) I I/O I/O I I I/O Function This is a chip select 0 pin used by MPU to select the SPC as an I/O device. This is an active-low pin. This is a chip select 1 pin to select when MPU inputs/outputs the data on DMA bus through SPC. This is an active-low pin. These pins are for the upper byte and parity bit of MPU data bus. When the CS0 input is valid, these pins serve as I/O ports for the SPC internal registers. When the CS1 input is valid, these pins serve as I/O ports for the DMA bus data. These pins are for the lower byte and parity bit of the MPU data bus. When the CS0 input is valid, these pins serve as I/O ports for the SPC internal registers. When the CS1 input is valid, these pins serve as I/O ports for the DMA bus data. These are address input pins to select the SPC internal registers. In the 80-series mode, this is a read signal input pin (IORD or RD) that MPU reads the SPC. This read signal pin is an activelow. In the 68-series mode, this pin functions as the control signal input (R/W) to control the read/write operation to the SPC. In the read operation, this pin is an active-high. In the write operation, this pin is an active-low. In the 80-series mode, this pin is a write signal input pin (IOWR or WR) that MPU writes to the SPC. This write signal input pin is active-low. In the 68-series mode, this pin function as the lower data strobe signal input (LDS) that MPU outputs when the lower byte of data bus is valid. The LDS pin is an active-low.
98, 97, 96, D15 95, 94, 93, to 92, 91 D8 99 UDP
89, 88, 87, D7 86, 85, 84, to 83, 82 D0 81 LDP
76, 75, 74, A4 73, 72 to A0 2 RD (R/W)
I
1
WR (LDS)
Write (lower data strobe)
I
(Continued)
5
MB86604L
(Continued)
Pin number 100 Symbol* BHE (UDS) Pin name Bus high enable (strobe) I/O I Function In the 80-series mode, this pin is used for input of the bus high enable signal (BHE) output from the MPU when the upper byte of the data bus is valid. The BHE pin is an active-low. In the 68series mode, this pin functions as the upper data strobe signal input pin (UDS) output from the MPU when the upper byte of the data bus is valid. The UDS pin is also an active-low. The INT and INT pins are the interrupt request signal output. The INT pins is used for the 80-series mode (an active-high pin), and the INT signal is used for the 68-series mode (an active-low pin). This input pin is used to select the type of the MPU and DMA buses. In the 80-series mode, a high level is input. In the 68series mode, a low level is input.
7
INT (INT) MODE
Interrupt request Mode
O
8
I
* : The pin symbols in parenthesis are the ones when the MODE input is "L".
3. DMA Interface
Pin number 52 Symbol* DREQ Pin name DMA request I/O O Function This is an output pin of DMA transfer request signal to the DMA controller. The data transfer between the SPC and memory via the DMA bus is requested. This pin is an active-high. This is a DMA acknowledge signal input pin output from the DMA controller that enables the DMA transfer. This pin is an active-low. When this pin is an active state, the DMA cycle (read/ write) is valid. These pins are the input/output pins of the upper byte and parity bit of the DMA data bus. When the signal input to the CS1 pin (pin 80) is valid, these pins are connected directly to the MPU data bus. These pins are the input/output pins of the lower byte and parity bit of the DMA data bus. When the CS1 (pin 80) input is valid, these pins are connected directly to the MPU data bus.
51
DACK
DMA acknowledge
I
48, 47, 46, DMD15 45, 44, 43, to 42, 41 DMD8 49 UDMDP
DMA data 15 to DMA data 8 Upper DMA data parity DMA data 7 to DMA data 0 Lower DMA data parity I/O read (DMA read/ write)
I/O
39, 38, 37, DMD7 36, 35, 34, to 33, 32 DMD0 31 27 LDMDP IORD (DMR/W)
I/O
I
In the 80-series mode, this pin (IORD or RD) is used for the input pin to output the data from the SPC to the DMA bus. This is an active-low pin. In the 68-series mode, this pin functions as a control signal input pin (DMR/W) to input/output the data to the SPC by the DMA controller. In the output operation, this pin is on the high-state (active-high state). In the input operation, this pin is on the low-state (active-low state). In the 80-series mode, this (IOWR or WR) is used for the input pin to input the DMA bus data to the SPC. In the 68-series mode, this pin functions as a DMA lower data strobe input (DMLDS) that DMA controller outputs when the lower byte of the DMA bus data is valid. Both IOWR and DMLDS pins are an active-low.
26
IOWR (DMLDS)
I/O write (DMA lower data strobe)
I
(Continued)
6
MB86604L
(Continued)
Pin number 50 Symbol* DMBHE (DMUDS) Pin name DMA bus high enable (DMA upper data strobe) I/O I Function In the 80-series mode, this pin is for the DMA bus high enable signal input pin (DMBHE) output from the DMA controller when the upper byte of the DMA data bus is valid. This is an active-low pin. In the 68-series mode, this pin functions as the DMA upper data strobe signal input pin (DMUDS) output from the DMA controller when the upper byte of data bus is valid. The DMUDS pin is also an active-low. In the 80-series mode, this pin is used for the DMA address 0 input pin output from the DMA controller. In the 68-series mode, a high level should be input to this pin. This is a DMA transfer permission signal input pin. When this pin is in active-state, the SPC does the DMA transfer. In case that this pin becomes inactive during the DMA transfer, the DMA transfer is paused on the block boundary. This pin is an active high.
30
DMA0
DMA address 0 Transfer permission
I
55
TP
I
* : The pin symbols in parenthesis are the ones when the MODE input is "L".
4. Others
Pin number 6 5 3, 14, 28 53, 64, 78 4, 10, 15 16, 21, 29 40, 54, 59 65, 66, 70 79, 90 23 Symbol* RESET CLK VDD VSS Pin name Reset Clock Power supply Ground I/O I I -- -- Function System reset input pin. The input reset active pulse width must have 4 times of the clock cycle at least. This is an active-low pin. Clock signal input pin. 20 MHz, 30 MHz, or 40 MHz can be applied as the input clock frequency. +5 V power supply pins. Ground pins.
TEST1
TEST
I
This pin is used to select the type of I/O buffer on SCSI data bus pins. In case that DBP DB7 - DB0 pins are used as an open, drain I/O, connect this pin to VSS. In case of three-state I/O, connect to VDD. This pin is used to select the type of I/O buffer on SCSI pins. In case that MSG, C/D, I/O, and ATN pins are used as an opendrain I/O, connect this pin to VSS. In case of three-state I/O, connect to VDD. This is a SCSI Timeout pin that indicates the SPC has been busy longer than the specified time. A high level is output on this pin if the SPC busy time exceeds the specified time. This pin can be used for the timeout counter. These are open pins. Those pins are not connected with the device internally. Those pins must be left open.
57
TEST2
TEST
I
24
TMOUT
TIMEOUT
O
25, 26
(OPEN)
(Open)
--
* : The pin symbols in parenthesis are the symbols when the MODE input is "L". 7
MB86604L
s BLOCK DIAGRAM
TMOUT
D15 to D8, UDP INT D7 to D0, LDP WR
RD
CS0
CS1
A4 to A0 BHE MODE
MPU interface
MSG C/D I/O ATN BSY SEL SCSI interface
Internal processor
Registers
DREQ DACK DMBHE
Timer
Receive MCS buffer (32 bytes)
DMA0 DMD15 to DMD8 UDMDP DMD7 to DMD0 LDMDP
Send MCS buffer (32 bytes)
REQ ACK
Transfer controller
Command user program memory (256 bytes)
DMA interface
RST
Phase controller
IOWR IORD
DB7 to DB0 DBP
Data register (32 bytes)
TP
8
MB86604L
s BLOCK DESCRIPTION
1. International Processor (Sequencer)
Performs sequence control between the SCSI bus phases.
Bus free phase
Information transfer phase
Information transfer phase: * * * * Command phase Data phase Status phase Message phase
Arbitration phase
Selection phase
2. Timer
Manages the SCSI time standards. Also, conducts the following time managements. * Time until the REQ or ACK signal is asserted for asychronous transfer data * Time until selection or reselection is retried * REQ and ACK timeout time during transfers: Asychronous transfer case Target: After the REQ is asserted, the time until the initiator asserts the ACK Initiator: After the ACK is asserted, the time until the target negates the REQ Synchronous transfer case Target: After the REQ is sent, the time until an ACK signal which makes the offset 0 is received from the initiator * SPC Timeout Manages the SPC timeout indicating the SPC busy time longer than the specified time.
3. Phase Controller
Controls the various phases executed by SCSI such as arbitration, selection/reselection, data in/out, command, status, and message in/out.
4. Transfer Controller
Controls the information (data, command, status, message) transfer phases executed by SCSI. The following two types of transfer phases are used. Asychronous transfer: Controls interlock (response confirmation format) between the REQ and ACK signals. Synchronous transfer: Controls a maximum 32-byte offset value for the data in or data out phase. The following two modes exist for the data phase. Program transfer: Uses data register (address 00/01) via the MPU interface DMA transfer: Uses DREQ and DACK signals via the DMA interface. The transfer parameter setting values for synchronous transfer (Transfer mode, transfer rate, transfer offset) can be strobe for individual ID device and are automatically established when the data phase is initiated. The number of transfer bytes is defined as block length x number of blocks.
9
MB86604L
5. Register
The main registers are listed. * Command register Command is specified by an 8-bit code. Specifies the program head address assigned to the user program memory for user program applications. * Chip status register Shows the chip's operating state, nexus counterpart ID, and data register state. * SCSI bus status register Shows the SCSI control signal state. * Interrupt status register Shows 8-bit code. * Command step register Shows 8-bit code indicating the command execution state. Error analysis can be performed by referring to the information in this register and the interrupt status register. * Group 6/7 command length setting register Sets the group 6/7 command length which is undefined by the SCSI standard. By setting the command length in this register, the SPC can determine the command length.
6. Receive-MCS Buffer
A receive only, 32-byte data buffer which stores information received via SCSI (message, command, status) M: Message, C: Command, S: Status
7. Send-MCS Buffer
A send only, 32-byte data buffer which stores information sent via SCSI (message, command, status)
8. Command User Program Memory
Program memory used for establishing programmable commands (256 bytes).
9. Data Register
FIFO-type data register which stores data in SCSI data phase (32 bytes).
10
MB86604L
s ABSOLUTE MAXIMUM RATINGS (See WARNING)
Parameter Power supply voltage* Input voltage* Output voltage* Operating ambient temperature Storage temperature * : VSS = 0 V WARNING: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Symbol VDD VI VO Top Tstg Rating Min. VSS - 0.5 VSS - 0.5 VSS - 0.5 -25 -40 Max. 6.0 VDD + 0.5 VDD + 0.5 +85 +125 Unit V V V C C
s RECOMMENDED OPERATING CONDITIONS
Parameter Power supply voltage *1 CLK "H" level input voltage *1 "L" level input voltage *1 "H" level output current *2 "L" level output current *2 Except SCSI and CLK pins SCSI pins CLK Except CLK pin Except SCSI pins SCSI pins Three-state Open-drain IOL Ta IOH VIL VIH Symbol VDD Value Min. 4.75 3.5 2.2 2.0 -- -- -- -- -- -- -- 0 Typ. 5.0 -- -- -- -- -- -- -- -- -- -- -- Max. 5.25 -- -- -- 1.5 0.8 -2.0 -8.0 -- +3.2 +48 +70 Unit V V V V V V mA mA mA mA mA C
Except SCSI pins SCSI pins
Operating ambient temperature
*1: VSS = 0 V *2: SCSI pins are DB7 to DB0, DBP BSY, SEL, RST, ATN, REQ, ACK, MSG, C/D, I/O , Note: The recommended operating conditions are the values recommended to ensure correct logic operation of the LSI. The standard values of the electrical characteristics (DC and AC characteristics) are guaranteed within the range of the recommended operating conditions.
11
MB86604L
s ELECTRICAL CHARACTERISTICS
1. DC Characteristics
(VDD = +5 V5%, VSS = 0 V, Ta = 0C to +70C) Parameter CLK "H" level input voltage Except SCSI and CLK pins SCSI pins "L" level input voltage CLK Except CLK pin
1
Symbol
Condition
Value Min. Max. 3.5 -- -- -- 1.5 0.8 -- VDD -- -- 0.4 0.5 +10 +10 45 48 55 -- 65 60 70
Unit V V V V V V V V V V V A A mA mA mA mA mA mA
VIH
--
2.2 2.0
VIL VHW IOH = -2.0 mA VOH IOH = -8.0 mA
-- --
-- -- 0.3 4.2 2.0
Input hysteresis of SCSI pins *
Except SCSI pins "H" level Three-state output voltage *1 SCSI pins Open-drain Except SCSI pins "L" level 1 output voltage * SCSI pins Input leakage current Input/output leakage current
-- VOL ILI ILOZ IOL = +3.2 mA IOL = +48.0 mA VSS VI VDD VSS VI VDD, See Note below CLK input = 20 MHz SPC operating clock = 10 MHz CLK input = 30 MHz SPC operating clock = 10 MHz All output pins opened CLK input = 40 MHz SPC operating clock = 13.3 MHz CLK input = 30 MHz SPC operating clock = 15 MHz CLK input = 20 MHz SPC operating clock = 20 MHz CLK input = 40 MHz SPC operating clock = 20 MHz
-- VSS -- -10 -10
Power supply current
IDD
, *1: SCSI pins are DB7 to DB0, DBP BSY, SEL, RST, ATN, REQ, ACK, MSG, C/D, I/O Note: Leakage current in the above spec indicates the following currents. (1) Leakage current at the high-Z state on the three-state output pins. (2) Leakage current at the output high-Z state (input state) on the bidirectional bus pins.
12
MB86604L
2. I/O Pin Capacitance
(VDD = VI = 0 V, f = 1 MHz, Ta = +25C) Parameter Input pin capacitance Output pin capacitance I/O pin capacitance Except SCSI pins SCSI pins Symbol CIN COUT CI/O Value Min. -- -- -- -- Max. 6 6 6 25 Unit pF pF pF pF
3. Load Conditions for AC Characteristics
(VDD = +5 V5%, VSS = 0 V, Ta = 0C to +70C) Non-SCSI pins
Measurement point
Pin Symbol INT, DREQ CL 60 pF
MB86604L
D15 to D8, UDP D7 to D0, LDP , DMD15 to DMD8, UDMDP 85 pF
Measurement pin CL
DMD7 to DMD0, LDMDP CL: Load capacitance
SCSI pins
Measurement point V DD
RL1 = 110
MB86604L Measurement pin
R L1
Load resistance Load capacitance
RL2 = 165 RL = 200 pF
R L2
CL
13
MB86604L
4. AC Characteristics
(1) System clock Value Parameter Clock cycle time (CLK) Clock "H" pulse width Clock "L" pulse width Clock rise time Clock fall time Symbol Position* tCLK twCKH twCKL tCR tCF A B C D E Min. 25.0 10.0 10.0 -- -- Max. 50.0 -- -- 10.0 10.0 ns ns ns ns ns Unit
* : The position number indicates the position in the waveform. Note: In case that the internal clock frequency and the input clock frequency are the same (i.e. when using the divided-by-one mode), the clock pulse width (for "H" and "L") must have at least 20 ns or longer.
B t wCKH t CF 3.5 V E
A t CLK D t CR
CLK
1.5 V C t wCKL
(2) System reset Value Parameter RESET "L" level pulse width Symbol Min. twRSL 4 tCLK Max. -- ns Unit
t wRSL
RESET
14
MB86604L
(3) MPU interface (80 series) * Register write timing Value Parameter Base signal Address (A4 to A0), BHE set up time Address (A4 to A0), hold time CS0 set up time CS0 hold time WR "L" level pulse width Data set up time Data hold time WR "L" WR "H" WR "L" WR "H" -- WR "H" WR "H" tsuA thA tsuCS0 thCS0 twWRL tsuD thD Symbol
Position*
Unit Min. 40 20 20 10 70 40 10 Max. -- -- -- -- -- -- -- ns ns ns ns ns ns ns A B C D E F G
* : The position number indicates the position in the waveform.
A4 to A0 BHE
A t suA B t hA
CS0
C E t wWRL D
t suCS0
t hCS0
WR
F t suD G t hD
D15 to D8, UDP
Data
D7 to D0, LDP
15
MB86604L
* Register read timing Value Parameter Base signal Address (A4 to A0), BHE set up time Address (A4 to A0), Hold time CS0 set up time CS0 hold time RD "L" level pulse width Data output defined time Data output disable time INT signal clear time for INT non-hold mode for INT hold mode RD "L" RD "H" RD "L" RD "H" -- RD "L" RD "H" RD "L" RD "H" tsuA thA tsuCS0 thCS0 twRDL tvD tDZ tDL tDL2 Symbol
Position*
Unit Min. 40 20 20 10 70 -- 10 -- -- Max. -- -- -- -- -- 70 -- 50
n tCLK + 50
A B C D E F G H I
ns ns ns ns ns ns ns ns ns
* : The position number indicates the position in the waveform.
A4 to A0 BHE
A t suA B t hA
CS0
C E t wRDL D
t suCS0
t hCS0
RD
F t vD G t DZ
D15 to D8, UDP
Valid data
D7 to D0, LDP
t DL
H
INT
t DL2* I
INT
*: t DL2 is determined by a rising edge of the strobe signal which reads the step code for the last interrupt source. Also, "n" indicates the division ratio.
16
MB86604L
* Register write timing (for external access) Value Parameter Base signal Address (A0), BHE set up time Address (A0), BHE hold time CS1 set up time CS1 hold time DMA data bus output delay time DMA data bus output undefined time MPU data DMA data bus output delay time WR "L" WR "H" WR "L" WR "H" WR "L" WR "H" -- tsuAE thAE tsuCS1 thCS1 tvDMD tWRDMD tDDMD Symbol
Position*
Unit Min. 40 20 20 10 -- 10 -- Max. -- -- -- -- 70 -- 40 ns ns ns ns ns ns ns A B C D E F G
* : The position number indicates the position in the waveform.
A0 BHE
A t suAE B t hAE
CS1
WR
D15 to D8, UDP D7 to D0, LDP
DMD15 to DMD8, UDMDP DMD7 to DMD0, LDMDP
6! 5, 4+" * ! 6 +,
t suCS1 t hCS1 t vDMD E F t WRDMD Data t DDMD G Valid data
C
D
17
MB86604L
* Register read timing (for external access) Value Parameter Base signal Address (A0), BHE set up time Address (A0), BHE hold time CS1 set up time CS1 hold time MPU data bus output enable time MPU data bus output disable time DMA data MPU data bus output delay time RD "L" RD "H" RD "L" RD "H" RD "L" RD "H" -- tsuAE thAE tsuCS1 thCS1 tZD tDZ tDMDD Symbol
Position*
Unit Min. 40 20 20 10 -- 10 -- Max. -- -- -- -- 70 -- 40 ns ns ns ns ns ns ns A B C D E F G
* : The position number indicates the position in the waveform.
A0 BHE
A t suAE B t hAE
CS1
t suCS1 C
RD
DMD15 to DMD8, UDMDP DMD7 to DMD0, LDMDP
E
t DZ
D15 to D8, UDP D7 to D0, LDP

D t hCS1 Data G t DMDD
F t ZD
Valid data
18
MB86604L
(4) MPU interface (68 series) * Register write timing Value Parameter Base signal Address (A4 to A0) set up time Address (A4 to A0) hold time CS0 set up time CS0 hold time R/W set up time R/W hold time UDS/LDS "L" level pulse width Data set up time Data hold time UDS/LDS "L" UDS/LDS "H" UDS/LDS "L" UDS/LDS "H" UDS/LDS "L" UDS/LDS "H" -- UDS/LDS "H" UDS/LDS "H" tsuA thA tsuCS0 thCS0 tsuRW thRW twDS tsuD thD Symbol
Position*
Unit Min. 40 20 20 10 20 20 70 40 10 Max. -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns A B C D E F G H I
* : The position number indicates the position in the waveform.
A4 to A0
A t suA B t hA
CS0
C D t suCS0 t hCS0
R/W
E F t hRW
t suRW
t wDS
G
UDS/LDS
H t suD I t hD
D15 to D8, UDP
Data
D7 to D0, LDP
19
MB86604L
* Register read timing Parameter Address (A4 to A0) set up time Address (A4 to A0) hold time CS0 set up time CS0 hold time R/W set up time R/W hold time UDS/LDS "L" level pulse time Data output confirmation time Data output disable time INT signal clear time for INT non-hold mode for INT hold mode Symbol
Position*
Value Min. 40 20 20 10 20 20 70 -- 10 -- -- Max. -- -- -- -- -- -- -- 70 -- 50
n tCLK + 50
Base signal UDS/LDS "L" UDS/LDS "H" UDS/LDS "L" UDS/LDS "H" UDS/LDS "L" UDS/LDS "H" -- UDS/LDS "L" UDS/LDS "H" UDS/LDS "L" UDS/LDS "H"
Unit ns ns ns ns ns ns ns ns ns ns ns
tsuA thA tsuCS0 thCS0 tsuRW thRW twDS tvD tDZ tDH tDH2
A B C D E F G H I J K
* : The position number indicates the position in the waveform.
A4 to A0
A t suA B t hA
CS0
C t suCS0 D t hCS0
R/W
E F t hRW G t wDS
t suRW
UDS/LDS
H t vD I
t DZ
D15 to D8, UDP
Valid data
D7 to D0, LDP
t DH J
INT
K * t DH2
INT
*: t DH2 is determined by a rising edge of the strobe signal which reads the step code for the last interrupt source. Also, "n" indicates the division ratio.
20
MB86604L
* Register write timing (for external access) Value Parameter Base signal Address (A0) set up time Address (A0) hold time CS1 set up time CS1 hold time R/W set up time R/W hold time DMA data bus output delay time DMA data bus output undefined time MPU data DMA data bus output delay time UDS/LDS "L" UDS/LDS "H" UDS/LDS "L" UDS/LDS "H" UDS/LDS "L" UDS/LDS "H" UDS/LDS "L" UDS/LDS "H" -- tsuAE thAE tsuCS1 thCS1 tsuRW thRW tvDMD tDSDMD tDDMD Symbol
Position*
Unit Min. 40 20 20 10 20 20 -- 10 -- Max. -- -- -- -- -- -- 70 -- 40 ns ns ns ns ns ns ns ns ns A B C D E F G H I
* : The position number indicates the position in the waveform.
A0
A t suAE B t hAE
CS1
C t suCS1 D t hCS1
R/W
UDS/LDS
D15 to D8, UDP D7 to D0, LDP
DMD15 to DMD8, UDMDP DMD7 to DMD0, LDMDP
6 5 4 36 25 ++, **! ," ' !
t suRW G t vDMD H t DSDMD Data I t DDMD Valid data
E
F t hRW
21
MB86604L
* Register read timing (for external access) Value Parameter Base signal Address (A0) set up time Address (A0) hold time CS1 set up time CS1 hold time R/W set up time R/W hold time Data output enable time Data output disable time DMA data MPU data bus output delay time UDS/LDS "L" UDS/LDS "H" UDS/LDS "L" UDS/LDS "H" UDS/LDS "L" UDS/LDS "H" UDS/LDS "L" UDS/LDS "H" -- tsuAE thAE tsuCS1 thCS1 tsuRW thRW tZD tDZ tDMDD Symbol
Position*
Unit Min. 40 20 20 10 20 20 -- 10 -- Max. -- -- -- -- -- -- 70 -- 40 ns ns ns ns ns ns ns ns ns A B C D E F G H I
* : The position number indicates the position in the waveform.
A0
A t suAE B t hAE
CS1
C t suCS1 D t hCS1
R/W
E F t hRW
t suRW
UDS/LDS DMD7 to DMD0, LDMDP DMD15 to DMD8, UDMDP
D15 to D8, UDP D7 to D0, LDP
22
A @ 6 57 +, *!
Data I t DMDD t ZD G H t DZ Valid data
MB86604L
(5) DMA interface The DMA access timing described in this section is not applicable in the following cases. During SCSI input, when the data buffer is EMPTY or when one byte is stored During SCSI output, when the data buffer is FULL or when 31 bytes are stored When a parity error is detected (target) When an error which pauses the transfer occurs at the SCSI interface * 80 series handshake mode (a) Write timing Value Parameter Base signal DACK "L" assert time DREQ "L" negate time DREQ "H" assert time (8 bit) DREQ "H" assert time (16 bit) IOWR "L" assert time DMBHE, DMA0 set up time DMBHE, DMA0 hold time IOWR "L" level pulse width DACK "H" negate time IOWR "H" Input data set up time Input data hold time IOWR "H" IOWR "H" tWRAK2 tsuDMD thDMD I J K 0 30 5 -- -- -- ns ns ns DREQ "H" DACK "L" DACK "H" DACK "H" DACK "L" IOWR "L" IOWR "H" -- IOWR "L" tRQAK tAKRQ tAKRQ1 tAKRQ2 tAKWR tsuDA thDA twWRL tWRAK1 Symbol
Position*
Unit Min. 0 -- -- -- 0 20 20 40 1 tCLK Max. -- 40 50
2 tCLK + 40
A B C C D E F G H
ns ns ns ns ns ns ns ns ns
-- -- -- -- --
* : The position number indicates the position in the waveform.
23
MB86604L
DREQ
t RQAK A B t AKRQ C t AKRQ1/2
DACK
D t AKWR H t WRAK1
I
t WRAK2
DMBHE DMA0
E t suDA G t wWRL
F t hDA
IOWR
J t suDMD K
t hDMD
DMD15 to DMD0 Data UDMDP, LDMDP
24
MB86604L
(b) Read timing Value Parameter Base signal DACK "L" assert time DREQ "L" negate time DREQ "H" assert time (8 bit) DREQ "H" assert time (16 bit) IORD "L" assert time DMBHE, DMA0 set up time DMBHE, DMA0 hold time IORD "L" level pulse width DACK "H" negate time IORD "H" Data output defined time Data output hold time IORD "L" IORD "H" tRDAK2 tvDMD thDMD I J K 0 -- 10 -- 40 -- ns ns ns DREQ "H" DACK "L" DACK "H" DACK "H" DACK "L" IORD "L" IORD "H" -- IORD "L" tRQAK tAKRQ tAKRQ1 tAKRQ2 tAKRD tsuDA thDA twRDL tRDAK1 Symbol
Position*
Unit Min. 0 -- -- -- 0 20 20 40 1 tCLK Max. -- 40 50
2 tCLK + 40
A B C C D E F G H
ns ns ns ns ns ns ns ns ns
-- -- -- -- --
* : The position number indicates the position in the waveform.
DREQ
t RQAK A B t AKRQ C t AKRQ1/2
DACK
D H t RDAK1
t AKRD
I
t RDAK2
DMBHE DMA0
E t suDA G t wRDL
F t hDA
IORD
J K
t vDMD
t hDMD
DMD15 to DMD0
Valid data
UDMDP, LDMDP
25
MB86604L
* 68 series handshake mode (a) Write timing Value Parameter Base signal DACK "L" assert time DREQ "L" negate time DREQ "H" assert time (8 bit) DREQ "H" assert time (16 bit) DMUDS/DMLDS "L" assert time DMR/W set up time DMR/W hold time DMUDS/DMLDS "L" level pulse width DACK "H" negate time DMUDS/DMLDS "H" Input data set up time Input data hold time DMUDS/DMLDS "H" DMUDS/DMLDS "H" tDSAK2 tsuDMD thDMD I J K 0 30 5 -- -- -- ns ns ns DREQ "H" DACK "L" DACK "H" DACK "H" DACK "L" DMUDS/DMLDS "L" DMUDS/DMLDS "H" -- DMUDS/DMLDS "L" tRQAK tAKRQ tAKRQ1 tAKRQ2 tAKDS tsuRW thRW twDSL tDSAK1 Symbol
Position*
Unit Min. 0 -- -- -- 0 20 20 40 1 tCLK Max. -- 40 50
2 tCLK + 40
A B C C D E F G H
ns ns ns ns ns ns ns ns ns
-- -- -- -- --
* : The position number indicates the position in the waveform.
DREQ
A t RQAK B t AKRQ C t AKRQ1/2
DACK
D H t DSAK1
t AKDS
I
t DSAK2
DMR/W
E t suRW G t wDSL F t hRW
DMUDS/DMLDS
J t suDMD K
t hDMD
DMD15 to DMD0
Data
UDMDP, LDMDP
26
MB86604L
(b) Read timing Value Parameter Base signal DACK "L" assert time DREQ "L" negate time DREQ "H" assert time (8 bit) DREQ "H" assert time (16 bit) DMUDS/DMLDS "L" assert time DMR/W set up time DMR/W hold time DMUDS/DMLDS "L" level pulse width DACK "H" negate time DMUDS/DMLDS "H" Data output defined time Data output hold time DMUDS/DMLDS "L" DMUDS/DMLDS "H" tDSAK2 tvDMD thDMD I J K 0 -- 10 -- 40 -- ns ns ns DREQ "H" DACK "L" DACK "H" DACK "H" DACK "L" DMUDS/DMLDS "L" DMUDS/DMLDS "H" -- DMUDS/DMLDS "L" tRQAK tAKRQ tAKRQ1 tAKRQ2 tAKDS tsuRW thRW twDSL tDSAK1 Symbol
Position*
Unit Min. 0 -- -- -- 0 20 20 40 1 tCLK Max. -- 40 50
2 tCLK + 40
A B C C D E F G H
ns ns ns ns ns ns ns ns ns
-- -- -- -- --
* : The position number indicates the position in the waveform.
DREQ
t RQAK A B t AKRQ C t AKRQ1/2
DACK
D H t DSAK1
t AKDS
I
t DSAK2
DMR/W
E t suRW G t wDSL F t hRW
DMUDS/DMLDS
J K
t vDMD
t hDMD
DMD15 to DMD0
Valid data
UDMDP, LDMDP
27
MB86604L
* Burst mode (80 series/68 series common) (a) Data register access cycle time (8 bit) Value Parameter Base signal Data register access cycle time 1 Data register access cycle time 2 Data register access cycle time 3 -- -- -- tDCY1 tDCY2 tDCY3 Symbol
Position*
Unit Min. tCLK 3 tCLK 4 tCLK Max. -- -- -- ns ns ns A B C
* : The position number indicates the position in the waveform.
IOWR/IORD DMUDS/DMLDS
A t DCY1 B t DCY2 C t DCY3
(b) Data register access cycle time (16 bit) Value Parameter Base signal Data register access cycle time 1 Data register access cycle time 2 -- -- tDCY1 tDCY2 Symbol
Position*
Unit Min. 4 tCLK 3 tCLK Max. -- -- ns ns A B
* : The position number indicates the position in the waveform.
IOWR/IORD DMUDS/DMLDS
B t DCY2 A t DCY1
28
MB86604L
* 80 series burst mode (a) Write timing Value Parameter Base signal DACK "L" assert time DREQ "L" negate time DREQ "L" DREQ "H" return time IOWR "L" assert time DMBHE, DMA0 set up time DMBHE, DMA0 hold time IOWR "L" level pulse width DACK "H" negate time Input data set up time Input data hold time DREQ "H" IOWR "L" -- DACK "L" IOWR "L" IOWR "H" -- IOWR "H" IOWR "H" IOWR "H" tRQAK tWRRQ tRQLH tAKWR tsuDA thDA twWRL tWRAK tsuDMD thDMD Symbol
Position*
Unit Min. 0 -- 0 0 20 20 40 0 30 5 Max. -- 55 -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns A B C D E F G H I J
* : The position number indicates the position in the waveform.
DREQ
A B t WRRQ C t RQLH
t RQAK
DACK
D t AKWR H
t WRAK
DMBHE DMA0
E t suDA F t hDA
t wWRL
G
IOWR
I t suDMD J
t hDMD
DMD15 to DMD0
Data
UDMDP, LDMDP
29
MB86604L
(b) Read timing Value Parameter Base signal DACK "L" assert time DREQ "L" negate time DREQ "L" DREQ "H" return time IORD "L" assert time DMBHE, DMA0 set up time DMBHE, DMA0 hold time IORD "L" level pulse width DACK "H" negate time Data output defined time Data output hold time DREQ "H" IORD "L" -- DACK "L" IORD "L" IORD "H" -- IORD "H" IORD "L" IORD "H" tRQAK tRDRQ tRQLH tAKRD tsuDA thDA twRDL tRDAK tvDMD thDMD Symbol
Position*
Unit Min. 0 -- 0 0 20 20 40 0 -- 10 Max. -- 55 -- -- -- -- -- -- 40 -- ns ns ns ns ns ns ns ns ns ns A B C D E F G H I J
* : The position number indicates the position in the waveform.
DREQ
t RQAK A B t RDRQ C t RQLH
DACK
D t AKRD H t RDAK
DMBHE DMA0
E t suDA G t wRDL F t hDA
IORD
I J
t vDMD
t hDMD
DMD15 to DMD0 UDMDP, LDMDP Valid data
30
MB86604L
* 68 series burst mode (a) Write timing Value Parameter Base signal DACK "L" assert time DREQ "L" negate time DREQ "L" DREQ "H" return time DMUDS/DMLDS "L" assert time DMR/W set up time DMR/W hold time DMUDS/DMLDS "L" level pulse width DACK "H" negate time Input data set up time Input data hold time DREQ "H" DMUDS/DMLDS "L" -- DACK "L" DMUDS/DMLDS "L" DMUDS/DMLDS "H" -- DMUDS/DMLDS "H" DMUDS/DMLDS "H" DMUDS/DMLDS "H" tRQAK tDSRQ tRQLH tAKDS tsuRW thRW twDSL tDSAK tsuDMD thDMD Symbol
Position*
Unit Min. 0 -- 0 0 20 20 40 0 30 5 Max. -- 55 -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns A B C D E F G H I J
* : The position number indicates the position in the waveform.
DREQ
t RQAK A B t DSRQ C t RQLH
DACK
D t AKDS H
t DSAK
DMR/W
E t suRW t wDSL G F t hRW
DMUDS/DMLDS
I t suDMD J
t hDMD
DMD15 to DMD0 UDMDP, LDMDP
Data
31
MB86604L
(b) Read timing Value Parameter Base signal DACK "L" assert time DREQ "L" negate time DREQ "L" DREQ "H" return time DMUDS/DMLDS "L" assert time DMR/W set up time DMR/W hold time DMUDS/DMLDS "L" level pulse width DACK "H" negate time Data output defined time Data output hold time DREQ "H" DMUDS/DMLDS "L" -- DACK "L" DMUDS/DMLDS "L" DMUDS/DMLDS "H" -- DMUDS/DMLDS "H" DMUDS/DMLDS "L" DMUDS/DMLDS "H" tRQAK tDSRQ tRQLH tAKDS tsuRW thRW twDSL tDSAK tvDMD thDMD Symbol
Position*
Unit Min. 0 -- 0 0 20 20 40 0 -- 10 Max. -- 55 -- -- -- -- -- -- 40 -- ns ns ns ns ns ns ns ns ns ns A B C D E F G H I J
* : The position number indicates the position in the waveform.
DREQ
t RQAK A B t DSRQ C
t RQLH
DACK
D t AKDS H
t DSAK
DMR/W
E t suRW G t wDSL F t hRW
DMUDS/DMLDS
I J
t vDMD
t hDMD
DMD15 to DMD0 UDMDP, LDMDP Valid data
32
MB86604L
(6) SCSI interface (as initiator) * Asynchronous transfer mode (a) Input timing (target initiator) Value Parameter Base signal REQ "H" negate time ACK "H" negate time REQ "L" assert time Input data set up time Input data hold time ACK "L" assert time 1 ACK "L" assert time 2 *2 ACK "L" REQ "H" ACK "H" REQ "L" REQ "L" REQ "L" REQ "H" tAKRQH tRQAKH tAKRQL tsuDB thDB tRQAK1 tRQAK2 Symbol
Position*1
Unit Min. 0 -- 10 10 20 -- -- Max. -- 60 -- -- -- 40
3 tCLK + 40
A B C D E F G
ns ns ns ns ns ns ns
*1: The position number indicates the position in the waveform. *2: The REQ "H" ACK "L" time (tRQAK2) is compared with (tRQAKH + tAKRQL + tRQAK1) and the longer value is chosen. Note: The input timing definition is not applied in the following cases. * When the data register is FULL in the data phase * When the final byte is being transferred
G t RQAK2
REQ
A t AKRQH B t RQAKH C t AKRQL F t RQAK1
ACK
D t suDB E t hDB
DB7 to DB0 DBP Data
33
MB86604L
(b) Output timing (initiator target) Value Parameter Base signal REQ "H" negate time ACK "H" negate time REQ "L" assert time Time from output data valid to ACK "L" assert *2 Output data hold time ACK "L" assert time ACK "L" REQ "H" ACK "H" -- REQ "H" REQ "L" tAKRQH tRQAKH tAKRQL tDBAK thDB tRQAK1 Symbol
Position*1
Unit Min. 0 -- 10
S * tCLK - 10
Max. -- 60 -- -- -- 40 ns ns ns ns ns ns
A B C D E F
2 tCLK --
*1: The position number indicates the position in the waveform. *2: "S" value is based on the asychronous set up time setting register (address 17h). Note: The output timing definitions are not applied when the data register is EMPTY in the data phase.
REQ
ACK
DB7 to DB0 DBP
' &
t RQAK2
*
t AKRQH
A
B t RQAKH
C t AKRQL
F t RQAK1
D t DBAK Valid data
E t hDB
D t DBAK Valid data
*: The REQ "H" ACK "L" time (tRQAK2) is defined by either longer of (tRQAKH + tAKRQL + tRQAK1) or (thDB + tDBAK) (see the output timing waveform).
34
MB86604L
* Synchronous transfer mode (a) REQ/ACK signal period Value Parameter Base signal ACK assert time *2 ACK negate time *2 REQ assert time REQ negate time REQ input cycle time 1 REQ input cycle time 2 -- -- -- -- -- -- tAKAP tAKNP tRQAP tRQNP tRQCY1 tRQCY2 Symbol
Position*1
Unit Min.
A * tCLK - 12 N * tCLK + 2
Max. -- -- -- -- -- -- ns ns ns ns ns ns
A B C D E F
20 20 1 tCLK 3 tCLK
*1: The position number indicates the position in the waveform. *2: "A" and "N" values are based on the transfer period register (address 0Dh) setting.
A t AKAP
B t AKNP
ACK
C t RQAP D t RQNP
REQ
E t RQCY1 F t RQCY2
35
MB86604L
(b) Input timing (target initiator) Value Parameter Base signal Input data set up time Input data hold time REQ "L" REQ "L" tsuDB thDB Symbol
Position*
Unit Min. 5 15 Max. -- -- ns ns A B
* : The position number indicates the position in the waveform.
REQ
A B t hDB A B t hDB
t suDB
t suDB
DB7 to DB0 DBP
Data Data
(c) Input timing (target initiator) Value Parameter Base signal Time from output data valid to ACK "L" assert *2 Output data hold time *2 -- ACK "L" tDBAK thDB Symbol
Position*1
Unit Min.
N * tCLK + 2 A * tCLK - 12
Max. -- -- ns ns
A B
*1: The position number indicates the position in the waveform. *2: "A" and "N" values are based on the transfer period register (address 0Dh) setting.
36
6** 5" 4 +! *,! , ! 660 55. 4433 ++$ ,
ACK
A t DBAK B t hDB A t DBAK B t hDB
DB7 to DB0 DBP
Valid data
Valid data
MB86604L
(7) SCSI interface (as initiator) * Asynchronous transfer mode (a) Input timing (initiator target) Value Parameter Base signal ACK "L" assert time REQ "H" negate time ACK "H" negate time Input data set up time Input data hold time ACK "L" assert time 1 ACK "L" assert time 2 *2 REQ "L" ACK "L" REQ "H" ACK "L" ACK "L" ACK "H" ACK "H" tRQAKL tAKRQH tRQAKH tsuDB thDB tAKRQ1 tALRQ2 Symbol
Position*1
Unit Min. 0 -- 0 10 20 -- -- Max. -- 60 -- -- -- 40
3 tCLK + 40
A B C D E F G
ns ns ns ns ns ns ns
*1: The position number indicates the position in the waveform. *2: The REQ "L" REQ "L" time (tAKRQ2) is compared with (tAKRQH + tRQAKH + tAKRQ1) and the longer value is chosen. Note: The input timing definition is not applied in the following cases. * When the data register is FULL in the data phase * When the final byte is being transferred
G t AKRQ2
REQ
A t RQAKL B t AKRQH C t RQAKH F t AKRQ1
ACK
D E t hDB
t suDB
DB7 to DB0 DBP
Data
37
MB86604L
(b) Output timing (target initiator) Value Parameter Base signal ACK "L" assert time REQ "H" negate time ACK "H" negate time Time from output data valid to REQ "L" assert *2 Output data hold time REQ "L" assert time REQ "L" ACK "L" REQ "H" -- ACK "L" ACK "H" tRQAKL tAKRQH tRQAKH tDBRQ thDB tAKRQ1 Symbol
Position*1
Unit Min. 0 -- 0
S * tCLK - 10
Max. -- 60 -- -- -- 40 ns ns ns ns ns ns
A B C D E F
2 tCLK --
*1: The position number indicates the position in the waveform. *2: "S" value is based on the asychronous set up time setting register (address 17h). Note: The output timing definitions are not applied when the data register is EMPTY in the data phase.
A @ ? 6 5 4 3 + *7 , !
REQ
A t RQAKL B t AKRQH
t AKRQ2
*
C t RQAKH
F t AKRQ1
ACK
D t DBRQ
E t hDB
D t DBRQ
DB7 to DB0 DBP
Valid data
Valid data
*: The ACK "L" REQ "L" time (tAKRQ2) is defined by either longer of (tAKRQH + tRQAKH + tAKRQ1) or (thDB + tDBRQ).
38
MB86604L
* Synchronous transfer mode (a) REQ/ACK signal period Value Parameter REQ assert time *2 REQ negate time *2 ACK assert time ACK negate time ACK input cycle time 1 ACK input cycle time 2 Symbol
Position*1
Unit Min.
A * tCLK - 12 N * tCLK + 2
Max. -- -- -- -- -- -- ns ns ns ns ns ns
tRQAP tRQNP tAKAP tAKNP tAKCY1 tAKCY2
A B C D E F
20 20 1 tCLK 3 tCLK
*1: The position number indicates the position in the waveform. *2: "A" and "N" values are based on the transfer period register (address 0Dh). See (8) for more setting values.
A t RQAP
B t RQNP
REQ
C t AKAP D t AKNP
ACK
E t AKCY1
F t AKCY2
39
MB86604L
(b) Input timing (initiator target) Value Parameter Base signal Input data set up time Input data hold time ACK "L" ACK "L" tsuDB thDB Symbol
Position*
Unit Min. 5 15 Max. -- -- ns ns A B
* : The position number indicates the position in the waveform.
ACK
t suDB A B t hDB t suDB A B t hDB
DB7 to DB0
Data Data
DBP
(c) Output timing (target initiator) Value Parameter Base signal Time from output data valid to REQ "L" assert *2 Output data hold time *2 -- REQ "L" tDBRQ thDB Symbol
Position*1
Unit Min.
N * tCLK + 2 A * tCLK - 12
Max. -- -- ns ns
A B
*1: The position number indicates the position in the waveform. *2: "A" and "N" values are based on the transfer period register (address 0Dh). See (8) for more setting values.
+!$ *! !" ++ **
REQ
A t DBRQ B t hDB A t DBRQ B t hDB
DB7 to DB0 DBP
Valid data
Valid data
40
MB86604L
(8) A/N/S values in the SCSI interface timing specification * Transfer period register (address 0Dh) and A/N values Transfer period register Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 A Prohibit 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 N Prohibit 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 Transfer period register Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 A 9 9 10 10 11 11 12 12 13 13 14 14 15 15 16 16 N 8 9 9 10 10 11 11 12 12 13 13 14 14 15 15 16
Note: The A and N values set in the register are the assert period and the negate period respectively (unit is clock cycles) For the AC characteristics, A/N use numerals. * Asynchronous setup time register (address 17h) setting and the S value. Asynchronous setup time register Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 1 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 2 3 4 5 6 7 8 S Asynchronous setup time register Bit 3 Bit 2 Bit 1 Bit 0 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 9 10 11 12 13 14 15 16 S
Note: The S (setup time) value established in the set up time register during asynchronous data transfers indicates the time from setting data in the data bus until the REQ/ACK signals are asserted. For the AC characteristics, S uses numerals. 41
MB86604L
s LIST OF REGISTERS
1. BASIC Control Registers (for write)
Address
Hex. A4 A3 A2 A1 A0
Register name Output data register (first)
Output data register (second)
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Direct control register (Reserved) SEL/RESEL ID register Command register Data block register (MSB) Data block register (LSB) Data byte register (MSB) Data byte register Data byte register (LSB) MC byte register Diagnostic control register Transfer mode register Transfer period register Transfer offset register Window address register
Bit 7 DO7 DO15 DC7 0 SI7 CM7 BL15 BL7 BY23 BY15 BY7 DG7 TM7 0 0 WA7
Bit 6 DO6 DO14 0 0 0 CM6 BL14 BL6 BY22 BY14 BY6 DG6 0 0 0 WA6
Bit assignment Bit 5 Bit 4 Bit 3 Bit 2 DO5 DO4 DO3 DO2 DO13 DO12 DO11 DO10 0 DO4 0 0 0 0 0 0 0 0 0 SI2 CM5 CM4 CM3 CM2 BL13 BL12 BL11 BL10 BL5 BL4 BL3 BL2 BY21 BY20 BY19 BY18 BY13 BY12 BY11 BY10 BY5 DG5 0 0 0 0 BY4 0 0 TP4 TO4 0 BY3 DG3 0 TP3 TO3 WA3 BY2 DG2 0 TP2 TO2 WA2
Bit 1 DO1 DO9 0 0 SI1 CM1 BL9 BL1 BY17 BY9 BY1 DG1 0 TP1 TO1 WA1
Bit 0 DO0 DO8 0 0 SI0 CM0 BL8 BL0 BY16 BY8 BY0 DG0 0 TP0 TO0 WA0
2. BASIC Control Registers (for read)
Address
Hex. A4 A3 A2 A1 A0
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
Bit 7 0 Input data register (first) DI7 1 Input data register (second) DI15 0 SPC status register SS7 1 Nexus status register NS7 0 Interrupt status register IS7 1 Command step register CS7 0 Data block register (MSB) BL15 1 Data block register (LSB) BL7 0 Data byte register (MSB) BY23 1 Data byte register BY15 Data byte register (LSB) 0 BY7 MC byte register 1 SCSI control signal status register SC7 0 Transfer mode register TM7 1 Transfer period register X 0 Transfer offset register X 1 Modified byte register X
Register name
Bit 6 DI6 DI14 SS6 NS6 IS6 CS6 BL14 BL6 BY22 BY14 BY6 SC6 X X X X
Bit assignment Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DI5 DI4 DI3 DI2 DI1 DI0 DI13 DI12 DI11 DI10 DI9 DI8 SS5 SS4 X SS2 SS1 SS0 NS5 X X NS2 NS1 NS0 IS5 IS4 IS3 IS2 IS1 IS0 CS5 CS4 CS3 CS2 CS1 CS0 BL13 BL12 BL11 BL10 BL9 BL8 BL5 BL4 BL3 BL2 BL1 BL0 BY21 BY20 BY19 BY18 BY17 BY16 BY13 BY12 BY11 BY10 BY9 BY8 BY5 SC5 X X X MB5 BY4 SC4 X TP4 TO4 BM4 BY3 SC3 X TP3 TO3 MB3 BY2 SC2 X TP2 TO2 MB2 BY1 SC1 X TP1 TO1 MB1 BY0 SC0 X TP0 TO0 MB0
Note: X indicates data is undefined. (0 or 1). 42
MB86604L
3. Initial Setting Window (for read/write)
Address
Hex. A4 A3 A2 A1 A0
Register name
Bit assignment Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CC7 CC6 CC5 CC4 CC3 CC2 CC1 CC0 0 0 0 0 0 0 OI2 0 OI1 OI0 AM7 AM6 AM5 AM4 AM1 AM0
10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1F
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1
0 Clock conversion setting 1 Self ID setting 0 Response mode setting 0 Selection/reselection retry setting 1 Selection/reselection timeout setting 0 REQ/ACK timeout setting 1 Asynchronous setup time setting 0 Parity error detection setting 1 Interrupt enable setting 1 DMA system setting 0 Automatic operation mode setting 1 SPC Timeout setting 1 Device revision indication
1 Selection/reselection mode setting SM7 SM6 SM5 SM4 SM3 SM2 SM1 SM0 SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0 ST7 0 IE7 0 ST6 0 0 0 ST5 0 IE5 ST4 0 IE4 ST3 AT3 IE3 0 ST2 AT2 0 IE2 0 ST1 AT1 IE1 0 ST0 AT0 IE0 0 RT7 RT6 RT5 RT4 RT3 RT2 RT1 RT0 PE7 PE6 PE5 PE4 PE3 PE1 PE0
0 Group 6/7 command length setting GL7 GL6 GL5 GL4 GL3 GL2 GL1 GL0 DM5 MD4 OM7 OM6 OM5 OM4 OM3 OM2 OM1 OM0 TO7 TO6 TO5 TO4 TO3 TO2 TO1 TO0 RV7 RV6 RV5 RV4 RV3 RV2 RV1 RV0
4. MCS Buffer Window
Address Hex. 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F A4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 For write SEND MCS buffer SEND MCS buffer SEND MCS buffer SEND MCS buffer SEND MCS buffer SEND MCS buffer SEND MCS buffer SEND MCS buffer SEND MCS buffer SEND MCS buffer SEND MCS buffer SEND MCS buffer SEND MCS buffer SEND MCS buffer SEND MCS buffer SEND MCS buffer For read RECEIVE MCS buffer RECEIVE MCS buffer RECEIVE MCS buffer RECEIVE MCS buffer RECEIVE MCS buffer RECEIVE MCS buffer RECEIVE MCS buffer RECEIVE MCS buffer RECEIVE MCS buffer RECEIVE MCS buffer RECEIVE MCS buffer RECEIVE MCS buffer RECEIVE MCS buffer RECEIVE MCS buffer RECEIVE MCS buffer RECEIVE MCS buffer
43
MB86604L
5. User Program Memory Window
Address Hex. 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D IE 1F A4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 For write User program memory User program memory User program memory User program memory User program memory User program memory User program memory User program memory User program memory User program memory User program memory User program memory User program memory User program memory User program memory User program memory For read User program memory User program memory User program memory User program memory User program memory User program memory User program memory User program memory User program memory User program memory User program memory User program memory User program memory User program memory User program memory User program memory
44
MB86604L
s LIST OF COMMANDS
SPC commands can be specified in the command register or the user program memory and divided into the following main groups. * Sequential commands Commands that perform a consecutive (including phase transitions) sequence operation. Can only be specified in the command register (1-byte). * Discrete commands Commands which perform operations from disassembled sequential commands. Can be specified in the command register (1-byte command) or the user program memory (1/2-byte command). * Special commands Can only be specified in the user program memory (1/2-byte command).
1. Initiator Commands
(1) Sequential commands No 1 2 3 4 5 6 7 8 00H 01H 02H 03H 04H 05H 06H 07H 0 0 0 0 0 0 0 0 Command code 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Operand (for program) (not possible) (not possible) (not possible) (not possible) (not possible) (not possible) (not possible) (not possible) Command name Select & CMD Select & 1-MSG & CMD Select & N-Byte-MSG & CMD Select & 1-MSG Select & N-Byte-MSG Send N-Byte-MSG Send N-Byte-CMD Receive N-Byte-MSG
45
MB86604L
(2) Discrete commands No 9 10 11 12 08H 09H 0AH 0BH 0 0 0 0 Command code 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Operand (for program) -- -- -- -- -- -- -- -- -- -- -- -- -- -- Select Select with ATN Set ATN Reset ATN Set ACK Reset ACK Send Data from MPU Send Data from DMA Receive Data to MPU Receive Data to DMA Send DATA from MPU Padding Send DATA from DMA Padding Receive Data to MPU Padding Receive Data to DMA Padding Send 1-MSG Send 1-MSG with ATN Receive MSG Send CMD Command name
13 0CH 0 14 0DH 0 15 16 17 18 19 20 21 22 23 24 25 26 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 0 0 0 0 0 0 0 0 0 0 0 0
0 Address of MSG sent 1 Address of MSG sent 0 SAVE address of MSG 1 Address of CMD sent
27 1CH 0
0 SAVE address of STATUS Receive STATUS
46
MB86604L
2. Target Commands
(1) Sequential commands No 1 2 3 4 5 6 7 8 9 10 11 12 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 0 0 0 0 0 0 0 0 0 0 0 0 Command code 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 Operand (for program) (not possible) (not possible) (not possible) (not possible) (not possible) (not possible) (not possible) (not possible) (not possible) (not possible) (not possible) (not possible) (not possible) Command name Reselect & 1-MSG Reselect & N-Byte-MSG Reselect & 1-MSG & Terminate Reselect & 1-MSG & Link-Terminate Terminate Link-Terminate Disconnect-Sequence Send N-Byte-MSG Receive N-Byte-CMD Receive N-Byte-MSG Reselect & N-Byte-MSG & Terminate Reselect & N-Byte-MSG & Link-Terminate Disconnect-Sequence 2
13 2CH 0
47
MB86604L
(2) Discrete commands No 14 15 16 17 18 19 20 21 22 23 24 25 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 0 0 0 0 0 0 0 0 0 0 0 0 Command code 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Operand (for program) -- -- -- -- -- -- -- -- Reselect Set REQ Reset REQ Disconnect Send Data from MPU Send Data from DMA Receive Data to MPU Receive Data to DMA Send 1 MSG Receive MSG Send Status Receive CMD Command name
0 Address of MSG sent 1 SAVE address of MSG 0 Send-status address 1 SAVE address of CDB
3. Common Commands
No 1 2 3 4 5 6 7 8 9 10 40H 41H 42H 43H 44H 45H 46H 47H 48H 49H 0 0 0 0 0 0 0 0 0 0 Command code 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 Operand (for program) (not possible) (not possible) (not possible) (not possible) (not possible) (not possible) (not possible) (not possible) (not possible) (not possible) Command name SOFTWARE RESET TRANSFER RESET SCSI RESET SET UP REG INIT DIAG START TARG DIAG START DIAG END COMMAND PAUSE SET RST RESET RST
48
MB86604L
4. Programmable Commands
The user program is stored in the user program memory and begins operation when the user program head address is written in the command register. Programmable commands are composed of discrete and special commands and have a command length of one (1) or two (2) bytes. * Command field assign Command type Command code (1st byte) Message, command, or status phases send command Discrete commands Message, command, or status phases receive command Data phase receive/send command or do not perform transfer command AND command TEST AND command Operand (2nd byte) Memory address of the data to be sent. Memory address of received data being stored. -- Data for AND operation or memory address of data for AND operation. Data for AND operation or memory address of data for AND operation. Data for COMPARE operation or memory address of data for COMPARE operation. Jump head address Memory address to be moved. User status code --
Special commands
COMPARE command Conditional branch command MOVE command STOP command NOP command
49
MB86604L
s SYSTEM CONFIGURATION EXAMPLE
1. 80-Series, Separate Bus Type
MB86604L
Oscillation circuit CLK
RESET circuit
RESET DB7 to 0 DBP
MODE INT TMOUT MPU
CS0 ACK CS1 ATN
Address decoder
A4 to A0
Address bus
REQ SCSI bus D15 to D0 MSG C/D I/O UDP LDP BHE RD WR DMD15 to 0 UDMDP LDMDP BSY DMA bus Data bus
DREQ SEL DACK DMBHE IORD RST IOWR DMA0 DMA controller Address DATA buffer memory
TP
50
MB86604L
2. 80-Series, Common Bus Type
MB86604L
Oscillation circuit CLK
RESET circuit
RESET DB7 to 0 DBP
MODE INT TMOUT MPU
CS1 ACK CS0 ATN
Address decoder
A4 to A0
Address bus
REQ SCSI bus D15 to D0 MSG C/D I/O UDP LDP BHE RD WR DMD15 to 0 UDMDP LDMDP BSY DMA bus Data bus
DREQ SEL DACK DMBHE IORD RST IOWR DMA0 DMA controller
TP
51
MB86604L
3. 68-Series, Separate Bus Type
MB86604L
Oscillation circuit CLK
RESET circuit
RESET DB7 to 0 DBP MODE INT TMOUT A0 CS0 ACK CS1 ATN Address decoder MPU
A4 to A1
Address bus
REQ SCSI bus D15 to D0 MSG C/D I/O UDP LDP R/W UDS LDS DMD15 to 0 UDMDP LDMDP BSY DMA bus Data bus
DREQ SEL DACK DMR/W DMUDS RST DMLDS DMA controller Address DATA buffer memory
DMA0 TP
52
MB86604L
4. 68-Series, Common Bus Type
MB86604L
Oscillation circuit CLK
RESET circuit
RESET DB7 to 0 DBP MODE
INT TMOUT A0 CS1 ACK CS0 ATN Address decoder MPU
A4 to A1
Address bus
REQ SCSI bus D15 to D0 MSG C/D I/O UDP LDP R/W UDS LDS DMD15 to 0 UDMDP LDMDP BSY DMA bus Data bus
DREQ SEL DACK DMR/W DMUDS RST DMLDS DMA controller
DMA0 TP
53
MB86604L
s ORDERING INFORMATION
Part number MB86604LPFV Package 100 pin Plastic LQFP (FPT-100P-M05) Remarks
54
MB86604L
s PACKAGE DIMENSION
100-pin Plastic LQFP (FPT-100P-M05)
16.000.20(.630.008)SQ
75
14.000.10(.551.004)SQ
51
1.50 -0.10 (MOUNTING HEIGHT) +.008 .059 -.004
+0.20
76
50
12.00 (.472) REF INDEX
15.00 (.591) NOM
Details of "A" part 0.15(.006)
100
26
0.15(.006) 0.15(.006)MAX
LEAD No.
1
25
"B"
+0.05
"A" 0.50(.0197)TYP 0.18 -0.03 +.003 .007 -.001
+0.08
0.40(.016)MAX 0.127 -0.02 +.002 .005 -.001
0.08(.003)
M
Details of "B" part 0.100.10 (STAND OFF) (.004.004)
0.10(.004)
0.500.20(.020.008) 0~10
C
1995 FUJITSU LIMITED F100007S-2C-3
Dimensions in mm (inches)
55
MB86604L
FUJITSU LIMITED
For further information please contact:
Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-88, Japan Tel: (044) 754-3763 Fax: (044) 754-3329 North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, U.S.A. Tel: (408) 922-9000 Fax: (408) 432-9044/9045 Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122 Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LIMITED #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220
All Rights Reserved. Circuit diagrams utilizing Fujitsu products are included as a means of illustrating typical semiconductor applications. Complete information sufficient for construction purposes is not necessarily given. The information contained in this document has been carefully checked and is believed to be reliable. However, Fujitsu assumes no responsibility for inaccuracies. The information contained in this document does not convey any license under the copyrights, patent rights or trademarks claimed and owned by Fujitsu. Fujitsu reserves the right to change products or specifications without notice. No part of this publication may be copied or reproduced in any form or by any means, or transferred to any third party without prior written consent of Fujitsu. The information contained in this document are not intended for use with equipments which require extremely high reliability such as aerospace equipments, undersea repeaters, nuclear control systems or medical equipments for life support.
F9702 (c) FUJITSU LIMITED Printed in Japan
56

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